1. Field of the Invention
The present invention relates to a voltage controlled oscillator and, more specifically, to a voltage controlled oscillator having a frequency corresponding to a control voltage and generating a clock signal having a predetermined amplitude.
2. Description of the Background Art
Recently, as the speed of internal operation of a semiconductor integrated circuit device has been improved, a PLL (Phase Locked Loop) circuit for generating an operation clock of a higher frequency has been required. In order to implement such a PLL circuit, a voltage controlled oscillator (hereinafter referred to as VCO) operating at a high frequency is necessary.
A differential VCO using a differential buffer has been proposed as a VCO operating at a high frequency (See Japanese Patent Laying-Open No. 9-214299).
The differential VCO includes, as shown in FIG. 14, a ring oscillator 51 and a bias circuit 52. Ring oscillator 51 includes a differential buffer train 51a including a plurality of differential buffers connected in series. An output of the differential buffer at the last stage of differential buffer train 51a is inverted and input to the differential buffer of the first stage. Delay time of each of the differential buffers varies in accordance with the control voltage VC, and amplitude of an output clock signal from each of the differential buffers varies in accordance with a bias voltage VB. Therefore, ring oscillator 51 oscillates at a frequency in accordance with the control voltage VC and outputs a clock signal of which amplitude corresponds to the bias voltage VB.
Bias circuit 52 includes a replica circuit of the differential buffer, and generates and applies to each differential buffer a bias voltage VB so that the amplitude of the output clock signal of the differential buffer does not vary dependent on the control voltage VC but has a prescribed amplitude in accordance with the reference voltage VR.
Therefore, the differential VCO enables setting of the amplitude of the clock signal to be smaller than the power supply voltage, and hence enables generation of a clock signal at a higher frequency.
In the conventional differential VCO, however, if a clock signal of a high frequency is to be obtained, the differential buffer comes to have smaller gain, which causes difficulty in causing oscillation of ring oscillator 51.
Further, control voltage VC and bias voltage VB are adapted to vary gradually to ensure stable operation of the differential VCO, and therefore at the time of power on, for example, a certain time period is necessary until the control voltage VC and the bias voltage VB attain to the normal values. In that period, however, it is more difficult for the ring oscillator to oscillate.